Timing references (e.g., clock signals) are often transmitted between components in a very-large-scale integration (VLSI) system. Distribution of a master clock signal (i.e., timing reference) in a VLSI system is typically achieved using a single distribution channel coupled between a transmitter and a receiver. As the channel length grows the magnitude of parasitic resistances and capacitances associated with the channel also grows. Such parasitic resistances and capacitances associated with the channel effectively act as a low-pass filter to the master clock signal being transmitted from the transmitter to the receiver. Thus, as the frequency of master clock signals increase so too does the power attenuation that occurs during transmission of the master clock signals across the channel.
At the receiver side, the received master clock signal must meet a minimum power threshold in order to be reconstructed. One approach for maintaining a power level sufficient to meet the minimum power threshold is to drive the master clock signal at a higher power. However, at higher frequencies, power attenuation is significantly more prominent and as such simply increasing the driving power (at such high frequencies) may not be sufficient to meet the minimum power threshold. Moreover, there is a desire to limit the driving power of the master clock signal in order to optimize performance of VLSI systems.